Revisiting Direct Tag Search Algorithm on Superscalar Processors

Modern microprocessors schedule instructions dynamically in order to exploit instruction level parallelism. It is necessary to increase instruction window size for improving instruction scheduling capability. However, it is di cult to increase the size without any serious impact on processor performance, since the instruction window is one of the dominant deciding processor cycle time. The reason why the instruction window is critical is that it is realized using content addressable memory (CAM). In general, RAMs are faster in access time and lower in power dissipation than CAMs. Therefore, it is desirable to replace the CAM instruction window by the RAM instruction window. This paper proposes such an instruction window, named explicit data forwarding instruction window. Simulation results show that the proposed instruction window achieves comparable performance with the conventional instruction window, while it could bene t from a shorter cycle time.